The subject matter of the present application is related to subject matter disclosed in U.S. patent application Ser. No. 08/486,796, which was filed on Jun. 7, 1995, and has now issued as U.S. Pat. No. 5,694,141 for a Computer System with Double Simultaneous Displays Showing Differing Display Images; in U.S. patent application Ser. No. 08/485,876, which was filed on Jun. 7, 1995, and has now issued as U.S. Pat. No. 5,673,416 for a Display FIFO Module including a Mechanism for Issuing and Removing Requests for DRAM Access; in U.S. patent application Ser. No. 08/487,120 which was filed on Jun. 7, 1995, and has now issued as U.S. Pat. No. 5,724,063 for a Computer System with Dual-Panel LCD Color Display; and in U.S. patent application Ser. No. 08/487,121, which was abandoned in favor of U.S. patent application Ser. No. 08/872,244, which was filed on Jun. 10, 1997, for a Computer System with Video Display Controller having Power Saving Modes now U.S. Pat. No. 5,886,689.
1.Field of the Invention
The present invention relates generally to a computer system with one or more display devices, such as a cathode ray tube (CRT) or liquid crystal display (LCD) for example. The display devices provide a user of the computer system with a visible display of computer data, such as text or graphics. More particularly, the present invention is in the field of a computer system having a graphics generator, and a video display controller (VDC) for such a computer system. Via a bus interface, the VDC receives image information, such as text or graphics generated by a processor (CPU) or retrieved by the CPU from another facility (such as a CD-ROM) of the computer system, and provides signals driving one or both of the CRT or LCD displays.
Still more particularly, the present invention is in the field of a VDC having a sequencer and controller (SEQC) for a dynamic random access memory (DRAM) of the VDC. Image information to be displayed on the CRT or LCD is stored in the DRAM in preparation to being transferred to a video memory of the first-in-first-out (FIFO) type. In addition to the FIFO and CPU, other devices of the computer system, such as a bit block transfer engine (bit-BLT) (i.e., a graphics generator) a request access to the DRAM. The SEQC arbitrates requests for access to the DRAM by the various devices of the computer system and prioritizes these requests for access to insure both that the display FIFO is not denied data for display and that most-efficient access to the DRAM is provided to the other devices of the computer system.
2.Related Technology
A conventional bus arbitrating circuit is known in accord with U.S. Pat. No. 4,453,214 (hereinafter, the '214 patent), issued Jun. 5, 1984 to Ralph L. Adcock. According to the '214 patent, a bus arbitrator and memory manager (BAMM) establishes a priority among competing operating units of a computer system. The BAMM sorts requests for access to the memory according to a priority, and allows the device with the highest priority access ahead of the other devices. It appears that once a device is allowed access to the memory, an interrupt of this access is not allowed when a request for access from another device with a higher priority is received by the BAMM of the '214 patent. When a device which has had memory access is finished with this access, it provides a "sign off" signal, thus allowing the BAMM to permit memory access to the device requesting access and having the highest priority.
With a BAMM of the type disclosed by the '214 patent, a display FIFO of a computer system could conceivably be denied access to the DRAM at a time when a display FIFO is nearly or completely out of information for display. Thus, continuity of operation of the display of the computer system could be interrupted. Understandably, this type of display interrupt would be concerning and confusing for a user of the computer system.
Another conventional graphics system with a graphics controller and DRAM controller is known in accord with U.S. Pat. No. 4,991,112 (hereinafter, the '112 patent), issued Feb. 5, 1991 to Jean-Michel Callemyn. According to the '112 patent, a DRAM controller receives refresh requests and requests for access to the DRAM in bursts, and arbitrates among the requests. During a display stage, after a preparatory read, the greatest priority is given to the display FIFO. A read of the DRAM in bursts may be interrupted when the FIFO is full. In this case, priority is given to a possible preparatory read. In the absence of a preparatory read request, a request by the CPU will be honored and access to the DRAM will be effected for the CPU. As soon as the FIFO makes a request for access, however, the CPU access will be interrupted, and the previously interrupted read in bursts for the FIFO with be resumed. During the line return stage, differing priorities are set for access to the DRAM. That is, refreshing the DRAM is given highest priority, followed by filling of the display FIFO. Third in priority is compliance with access requests from the graphics processor, and then accesses for the CPU. However, other than the interrupt described above, the '112 patent is not believed to allow interruption of an access to the DRAM once this access is allowed. Additionally, the interrupt allowed by the '112 patent is an inherent interrupt necessary to prevent data of the FIFO from being overwritten by new data because the FIFO is full.
Yet another conventional DRAM refresh controller with a bus arbitration scheme is known in accord with U.S. Pat. No. 5,345,577 (hereinafter, the '577 patent), issued Sep. 6, 1994, to Tzoyao Chan and Milton Cheung. According to the '577 patent, a cache controller is provided with both burst and hidden refresh modes. Refresh requests are counted but not acted upon by allowing memory access until a certain number of these requests are received. On the other hand, hidden refreshes are done with no hold signal being sent to the CPU while the refresh is done. Until the refresh is completed local memory access but not remote memory access is allowed. Consequently, the CPU is denied memory access during a hidden refresh, but will not expect immediate access to the memory anyway so that the hidden refresh does not interfere with CPU operation. Interruption of memory access once granted does not appear to be a feature of this patent.
Taking general considerations into account, in a graphics controller, such as a VDC generally described above, arbitrating DRAM interface (access) among the several devices of the system is the most critical portion of the controller. Access to the DRAM dictates how and when devices such as the bit-BLT engine, display FIFO, and the local bus (that is, the CPU) have access to the DRAM. Access requests by the CPU and bit-BLT engine are mutually exclusive, and will not occur simultaneously. Ordinarily, whenever access to the DRAM is discontinued for one device and allowed for another device, a new page of the DRAM must be accessed. That is, the DRAM may be visualized as a two-dimensional array of memory locations. This memory uses rows and columns of memory locations (or memory cells) with a row pointer and a column pointer. As long as memory access is made to a single row of the memory, with the column pointer simply moving along the row as data is written to or read from address locations of the row, then a single-page access to the memory is effected, and no page break is necessary. However, when another row (i.e., another page) of the memory must be accessed, a pre-charge sequence must be run in preparation to accessing the next row of memory locations. This pre-charge sequence takes time so that a multiple-page access to the memory is not nearly as efficient as a single-page access in terms of the amount of data written into or read from the memory during the time interval of such a memory access.
Thus, page-mode access to the DRAM is much more efficient in terms of time utilization than is random access to the DRAM because of the many page breaks required for random access. When page-mode is not maintained for the DRAM, then at least one preparatory pre-charge cycle must be conducted to allow access to another different page of the DRAM in addition to the time interval required to write the data to or read the data from the memory cells. When access is allowed to the DRAM for the bit-BLT, these accesses will ordinarily be multi-page accesses which consume considerable time, but a request for this access does not require that immediate access to the DRAM be granted. On the other hand, CPU (local bus) access to the DRAM is usually a single-page access, requires considerably less time than a bit-BLT access, and also does not require that a request result in immediate access. However, when the CPU is required to wait for DRAM access, the system throughput is decreased and the WINMARKS (industry standard performance bench marks) for the computer system also are decreased. Further, the display FIFO of a graphics controller also requests DRAM access, and may be envisioned as a storage tank of water (data) draining at a uniform rate from the bottom, and only occasionally being refilled from the top. The display FIFO stores image information to be sent to the display devices (i.e., to the CRT or LCD, for example). The rate of drainage of the data from the display FIFO depends on the mode of display operation. If the display is being operated in a gray-scale mode which requires four bits per pixel, then the display FIFO will not drain very fast. On the other hand, if the user is operating the display in a color mode, then each pixel of the display may require eight bits, or sixteen bits, or possibly more than sixteen bits of information; and the display FIFO will drain correspondingly faster.
The display FIFO refills much faster than it drains. But refilling may be intermittent and interrupted for the allowance of other activities requiring access to the DRAM. Further, it must be understood that while the FIFO is being refilled, complete double-words of data must be input from the DRAM. If there is insufficient room at the top of the display FIFO to accept all of the last complete double-word of data being input at a particular time, then some of the existing data will be overwritten and lost. Conventionally, a FIFOLO request (a low priority request for DRAM access) is issued by the display FIFO to the DRAM controller as soon as the display FIFO has room at the top for at least one double-word of new data without overwriting existing data waiting to be sent to the display device.
Consequently, one or more accesses to the DRAM may be granted to the display FIFO in response to the FIFOLO request. This request is not cleared until the FIFO is filled. If the display FIFO is not adequately refilled in response to the FIFOLO request, then as soon as the display FIFO starts to write its last double-word of data to the display a FIFOHI request for access to the DRAM will be issued. This FIFOHI request will be honored immediately. Again, the FIFOHI request will not be cleared until the FIFO is filled completely. Consequently, a conventional DRAM controller will clear both FIFOLO and FIFOHI simultaneously after a FIFOHI request has been issued. Again, these requests for DRAM access would conventionally not be cleared until the FIFO is completely filled with fresh data.
FIG. 1, line 1, depicts a timing diagram showing an idealized sequence of accesses to a DRAM of a VDC alternating between a display FIFO and a bit-BLT engine. Line 2 of this FIG. 1 also shows an idealized sequence of accesses to the DRAM by a display FIFO and the CPU. These idealized timing diagrams show that neither the bit-BLT or CPU is required to wait for DRAM access, that the DRAM has no idle time, and that the accesses granted are relatively long for the bit-BLT so that multi-page accesses can be accomplished. Conventional computer system graphics controllers do not achieve such idealized management of DRAM access.
Moreover, in an actual computer system graphics controller (i.e., a VDC), the sequencing of the requests for access to the DRAM and the accesses to the DRAM actually granted are not idealized. Accordingly, hypothetical FIG. 2 (designated as prior art) depicts a timing diagram as might be experienced in an actual conventional computer system graphics controller. Viewing FIG. 2, the first of the three time lines of this graph respectively shows requests for access to the DRAM from the CPU. The next two lines show access requests from the display FIFO: first on a low priority basis (FIFOLO)--indicating that the display FIFO is sufficiently depleted of display information that at least one double-word of new information can be written to this FIFO without overwriting existing data; and secondly, on a high priority basis (FIFOHI)--indicating that the display FIFO is using its last double-word of information and is at risk of running out of information to be provided to the user by means of the display device (i.e., the CRT or LCD, for example). These FIFOLO and FIFOHI requests are not cleared (i.e., removed or discontinued) until the display FIFO is granted DRAM access and the FIFO is completely filled with data. In this conventional graphics controller, access to the DRAM at the highest priority is allowed to a display FIFOHI request, even interrupting an access already granted to the CPU or to another device of the computer system.
Considering FIG. 2, during interval #1, the CPU is granted DRAM access and signs off. During interval #2, the DRAM is idle. The beginning of interval #3 indicates the start up of the display graphics process with the display FIFO empty, and the simultaneous issuance of a FIFOLO and FIFOHI request. The FIFOHI request is honored, but these requests (FIFOLO and FIFOHI) are not cleared until the display FIFO is completely filled with data. As a result, the beginning of interval #4 indicates a request from the CPU for DRAM access which will not be honored until the FIFOHI request is cleared. Interval #4 indicates waiting time for the CPU. The end of interval #4 indicates the simultaneous clearing of both FIFOLO and FIFOHI, and the beginning of interval #5 during which the CPU is finally granted DRAM access. Interval #9 indicates the issuance of a FIFOLO request from the display FIFO for DRAM access. Because insufficient data is provided to the display FIFO in response to the FIFOLO request (another device, such as the bit-BLT, for example, may be making DRAM access so that the FIFOLO request in not sufficiently honored), the display FIFO issues a FIFOHI request at the beginning of interval #10. This FIFOHI request is honored immediately during interval #10. However, another interval (interval #10) results during which the CPU is denied access to the DRAM. At the end of interval #10 the FIFOLO and FIFOHI requests are both cleared simultaneously, and the CPU is granted DRAM access.
Moreover, FIG. 2 shows that the conventional arbitration scheme results in the DRAM sometimes being idle (intervals 2, 6, and 8), and in either the CPU or display FIFO waiting for access to the DRAM (intervals 4, 9, and 10). Once a FIFOHI request is made, the CPU is be required to wait until the display FIFO is completely filled before access to the DRAM can be granted to the CPU, even though the display FIFO may have received enough data that there is no longer an immediate risk of its running out of data for the displays. This conventional graphics controller both fails to maintain page mode for the DRAM, and also decreases the throughput rate for the computer system.
Accordingly, a long-felt need has been recognized for a more efficient and effective way of arbitrating access to the DRAM of a graphics controller. To address that need, the above-identified Chee et al. application describes an arrangement in which DRAM access accorded a display FIFO in response to a high-priority request ordinarily lasts only until the FIFO's data level exceeds a relatively low threshold, not until it is completely filled. This reduces access delay for other devices that also need quick access.